For reasons of scaling, the use of planar MOSFET structures in device generations with a 65 nm design rule and smaller is becoming more and more complicated due to so-called short channel effects.
An improvement of device characteristics can be obtained by application of a finFET structure.
In a finFET, on top of an insulating layer a (relatively narrow) silicon line (a fin) is created between a source region and a drain region to serve as a channel. Next, a line-shaped control gate is created which crosses the fin. The control gate, which is separated from the fin by a thin gate oxide film surrounds (in cross-section) both the sidewalls and the top of the fin, which allows for a relatively large field effect by the gate on the fin channel.
For Flash memory, an application of a finFET structure as described above has been disclosed in US2005/013983A1. Between the control gate and the fin material a charge trapping layer stack is positioned. Here, the charge trapping stack is positioned on top of the fin. The control gate layer abuts the profile of the charge trapping stack, and also covers the sidewalls of the fin so as to form sidewall transistors.
Disadvantageously, during the manufacturing of prior art finFET flash memory devices, creation of the fin structures and the charge trapping stack on top of them requires lithographic processing with relatively high accuracy to ensure that respective dimensions of fin and charge trapping stack have a minimal variation, since such dimensional variations would strongly influence electronic properties of the finFET memory device.
Moreover, the relatively small contact area between the fin channel and the charge trapping stack results in relatively small currents during sensing (reading) of the memory device and additional amplification of signals may be required. Circuitry for amplification disadvantageously requires an additional footprint on the semiconductor substrate. For such prior art devices with, in particular, relatively small fin dimensions, the lower level of current per cell adversely limits the speed of the device.